MCG Reports
Cost Modeling of Display Technologies Utilizing CMOS Backplanes
(Integrated Circuit Backplane Costs for 11 Alternative Designs)
by David Armitage, Steve Jurichich, Charles McLaughlin and Larry Ragle
___________________________________________________
This study and spreadsheet cost model compare fabrication costs of more than 10 miniature imager device (MID) designs that use CMOS backplanes, imagers on a chip designed for use in projection and personal displays. The study compares both the current costs for SVGA definition imagers as well as the projected costs for future high definition SXGA devices.
WHO SHOULD BUY
The study and cost model are a unique and important resource for buyers, technologists, and marketeers of the new projection and personal display markets. For buyers of the new technologies the report and cost model provide detailed inside information on competitive costing. For makers of miniature imagers they provide competitive cost benchmarking and give an inside view of foundry costs.
The explosive growth of the desktop projection market and the emergence of products based on personal displays have spurred interest in a new generation of miniature imaging devices, essentially electronic displays built on the face of an integrated circuit chip. While Japanese manufacturers such as Seiko Epson and Sony have taken the early lead with devices based on poly-silicon on quartz backplanes, more than 10 U.S. companies are now introducing competitive products.
The study and model are a unique and important resource and a must read for technologists and marketeers in the projection and personal display markets. For makers of miniature imagers it provides cost benchmarking and gives an inside view of foundry costs.
The study examines the costs at three levels: IC backplane costs for each technology including special CMOS and additional processing, costs of fabricating the imager device, and the total system cost of a personal viewer module. The analysis uses a rigorous bottoms up approach, constructing the wafer and chip costs using a spreadsheet model developed at Stanford University, Sematech statistics for equipment and processing cost, and a University of California study to establish yields and defect rates. A 6 inch fab with 0.8 µm capability is used as the basis.
The costs for both currently available configurations as well as projected future high definition products are compared. Foundry costs can be modeled with or without depreciation
SCOPE OF MID TECHNOLOGIES
The study and model provide detailed assumptions and cost models for backplane costs for the following designs.
Class |
Type |
Company |
Microelectromechanical Structures (MEMs) |
Grating Light Valve |
Silicon Light Machines (Echelle) |
|
Digital Micromirror Device (DMD) |
Texas Instruments |
|
Diffractive Elastomeric |
Fraunhofer Institute |
Active Matrix Liquid Crystal |
Polysilicon, transmissive nematic |
Seiko Epson, Sony, Sarif |
|
Transferred silicon, transmissive nematic |
Kopin |
|
Crystalline silicon, PDLC |
Raychem-Hitachi |
|
Crystalline silicon, ferroelectric LC |
Displaytech |
|
Crystalline silicon, reflective nematic |
Spatialight |
|
Crystalline silicon, reflective nematic, diffractive color |
MicroDisplay |
Emissive |
Active matrix electroluminescent (AMEL) |
Planar Systems |
|
Field Emission Displays (FED) |
Micron Display Technology |
CONTENTS
View the table of contents for this report Table of Contents
View a List of Tables for this report
View a List of Figures for this report
MCG PERSONNEL - About the authors
Dr. Armitage is a consultant and engineering physicist specializing in display technology and electro-optics. Dave has an extensive background in modeling display devices and systems. Recent publications include SPIE articles on liquid crystal projection displays and silicon chip based imaging devices.
Chuck McLaughlin is a flat panel display technology and market consultant who has published a variety of reports and articles about the AMLCD business. Mr. McLaughlin specializes in defining opportunities and developing market strategy.
Larry Ragle is a leading technologist in semiconductors. Mr. Ragle is known primarily for the invention and development of the silicon vertical MOS power transistor, leading commercialization programs at Siliconix, Intersil, and Solitron Devices. His interest in miniature imaging technology began in 1994 with his involvement in an FED development initiative.
SUBSCRIPTION INFORMATION
The Report: The 75 page report includes 6 graphs, 10 figures, and 27 tables. One bound copy is furnished to each subscriber. The Report is now available.
The Model: The model is a Microsoft Excel 7.0 spreadsheet and is provided on a 3.5 inch floppy disc for Pcs. MAC format is optional. Electronic transfer is optional.
Price: Study and model, purchased together: $7,500. If purchased separately, the study price is $2,500 and the model price is $6,000. Extra copies will be provided for an additional charge of $375.
To Subscribe: Please forward your shipping address with your check or purchase order to McLaughlin Consulting Group, Fax 650 319 1805. Contact Chuck McLaughlin for more information.