McLaughlin Consulting Group - Human Factors | Microdisplays

MCG Reports

Cost Modeling of Display Technologies Utilizing CMOS Backplanes
(Integrated Circuit Backplane Costs for 11 Alternative Designs)
by David Armitage, Steve Jurichich, Charles McLaughlin and Larry Ragle

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Table of Contents

I. Introduction and Scope		6
II. Cost Model Methodology		8
	Introduction	8
	Incremental process Cost	9
	Process Yield Methodology for Wafer Processing	12
III. CMOS Process Flows		14
	CMOS Process General Considerations	14
	Yields and Defect Densities of CMOS Processing	18
IV. Display Process Flows		20
	Introduction	20
	1. Silicon Light Machines GLV	21
	2. Hertz Institute Deformable Mirror	25
	3. Texas Instruments Digital Micromirror Device	26
	4. Displaytech FLC	28
	5. Spatialight c-Si LCD	31
	6. MicroDisplay c-Si LCD	32
	7. Kopin x-Si LCD	34
	8. Seiko-Epson p-Si LCD	34
	9. Raychem/Hitachi PDLC	35
	10. Planar Systems AMEL	35
	11. Micron Technology FED	37
V. Die Cost Comparisons of Display Technologies		41
VI. Spreadsheet Cost Model Summaries		44
VII. Cost Sensitivity to Wafer process Flows and Yield Assumptions		55
VIII. Miniature Imaging Device Module Costs Compared		61
References		64
Appendix		66

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